1. Field of the Invention
The present disclosure generally relates to multi-gate FETs and to a method of forming such a FET, and, more particularly, to advanced multi-gate FETs, e.g., NW FETs or FinFETs, connected in parallel, and to a method of forming such a FET.
2. Description of the Related Art
In modern electronic technologies, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the ongoing demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than one micrometer, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than any discreet circuit composed of independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors) and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area, wherein typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a FET is that of an electronic switching element, controlling a current through a channel region between two junction regions, referred to as source and drain, by a gate electrode, which is disposed over the channel region and to which a voltage relative to source and drain is applied. In common FETs, the channel region extends along a plane between the source and drain regions, such FETs often being referred to as “planar FETs.” Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON state” and a non-conducting state or “OFF state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called “the threshold voltage”), therefore, characterizes the switching behavior of the FET and it is an issue to keep variations in the threshold value level low for implementing a well-defined switching characteristic. However, as the threshold voltage depends nontrivially on the transistor's properties, e.g., materials, dimensions etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine-tuning during the fabrication process, which makes the fabrication of advanced semiconductor devices increasingly complex.
For several decades during which the size of individual FETs has steadily decreased, planar transistors represented the core building blocks of ICs. However, with FETs steadily decreasing in size, it was observed that planar FETs more and more suffer from undesirable effects once the channel length of a FET entered the same order of magnitude as the width of the depletion layer of the source/drain regions. For strongly scaled FETs, for example, the OFF state leakage current (i.e., the leakage current during the OFF state) increased with the idle power required by the device. Accordingly, these deteriorating effects appearing at small scales and being associated with short channel lengths are frequently referred to as so-called “short-channel effects.”
As opposed to planar FETs, in which the channel region substantially extends in a single plane between the source and drain regions and on which plane a single gate electrode is disposed, the channel region of multi-gate transistors has a multi-dimensional configuration, where the channel region is surrounded by a gate disposed over more than one surface. In general, multi-gate transistors provide a better electrical control over the channel, allowing a more effective suppression of OFF state leakage currents. On the other hand, multi-gate transistors have an enhanced current in the ON state such that lower power consumption and enhanced device performance may be achieved by employing multi-gate transistors. Furthermore, as multi-gate transistors represent non-planar devices, it is even possible to fabricate more compact devices in comparison to conventional planar transistors, therefore, enabling higher transistor density and smaller overall microelectronic devices.
An example of a multi-gate transistor is given by a FinFET device in which a fin-like structure formed of semiconductor material extends between source and drain junctions, while a gate electrode is partially wrapped around the fin-like structure. The fin-like structure generally has a cross-section similar to a triangle or rectangle. A so-called dual gate configuration is realized upon the gate electrode being disposed over two opposing sidewalls of the fin-like structure. A so-called tri-gate configuration is realized upon the gate electrode being formed over two opposing sidewall surfaces and an upper surface of the fin-like structure.
Another possibility of multi-gate transistors is provided by nanowire (NW) transistors or NW FETs. In NW transistors, a current flows through the nanowire or is pinched off under the control of a voltage applied to a gate electrode surrounding the nanowire. With the nanowire providing the channel of the NW transistor, a so-called “gate all around” transistor is realized. However, due to the small size of the nanowire, single nanowires in general do not carry enough current to represent an efficient transistor. Therefore, a structure consisting of an array of several (up to 225) doped silicon nanowires, each 30 nm in diameter and 200 nm tall, vertically linking two platinum contact planes for forming source and drain junctions of the transistor, was proposed. Herein, besides having a narrow arrangement of nanowires, a single 40 nm-thick chromium layer surrounding each nanowire midway up its length was used for forming the gate electrode.
It turned out that, for current strongly-scaled semiconductor devices, a very high number of nanowires have to be connected in parallel in order to provide a high enough total amount of drive current, which may not be provided by presently-known NW transistors. The reason is that the total amount of current available for operation is substantially limited by the small dimensions of the nanowire. For strongly-scaled semiconductor devices formed by multiple nanowires, there is, at the moment, no reliable method/process available to place a plurality of nanowires close to each other with a high enough accuracy to allow for a strongly-scaled semiconductor device providing a high enough total drive current.
Therefore it is desirable to provide an advanced semiconductor device and a method of forming an according semiconductor device, wherein at least one of the above-described issues are addressed, if not avoided.